1. Field of the Invention
The present invention relates to thin-film elements using a thin-film semiconductor, particularly a thin-film transistor (hereinafter abbreviated as TFT). The invention also relates to semiconductor devices such as electro-optical devices and semiconductor circuits using such a thin-film transistor.
2. Description of the Related Art
In recent years, with the spread of liquid crystal displays (LCDs), active matrix liquid crystal displays (AMLCD) are required to be improved in performance. However, there have been pointed out various problems that obstruct the improvement in performance.
Increase in operation speed is one item of the required improvements in performance. However, it is known that the self-heating of a TFT increases as the operation speed is increased. This is also problematic in ICs.
In particular, in circuits, such as driver circuits (a buffer, an analog switch, etc.), in which large current needs to flow and which are hence constituted of TFTs having a very long channel width (W), each constituent TFT exhibits a high degree of self-heating and the temperature of the entire circuit may become abnormally high. There is a report that the temperature increased to as high as several hundred degrees centigrade in certain situations.
The self-heating varies or deteriorates the characteristics of a TFT and makes it difficult to realize highly reliable products. To suppress self-heating of a TFT having a long channel width, the following conventional technique has been proposed.
FIG. 2A is a schematic top view showing an active layer (thin-film semiconductor layer) of a TFT. FIGS. 2B-2D are sectional views taken along lines A-A', B-B', and C-C' in FIG. 2A, respectively.
In FIG. 2A, reference numeral 201 denotes a substrate having an insulative surface, and 202 and 203 denote a pair of impurity regions formed by adding an n-type or p-type impurity to an active layer that is a semiconductor thin film. The impurity regions 202 and 203 serve as source/drain regions.
The pair of impurity regions 202 and 203 are formed in a self-aligned manner by using a gate electrode 204 as a mask. The region under the gate electrode 204 is doped with neither of those impurities and channel forming regions 205 are formed there (see FIGS. 2B and 2D).
The conventional structure shown in FIGS. 2A-2D has a feature that openings 206 are formed in the active layer in patterning it and the channel forming region is divided into a plurality of parts. That is, substantially a plurality of TFTs are arranged in parallel.
The openings 206 function as heat sinks for allowing escape of Joule heat generated in the channel forming regions 205. That is, this technique allows Joule heat generated in the channel forming regions 205 to escape efficiently, thereby reducing the amount of heat generated in the TFT and in turn securing its reliability.
In the conventional technique shown in FIGS. 2A-2D, the regions 206 serving as the heat sinks are filled with a gate insulating film 207. Therefore, the channel forming regions 205 are insulated from each other by the gate insulating film 207.
Therefore, Joule heat generated in the channel forming regions 205 is introduced to the gate insulating film (typically a silicon oxide film) 207. However, the efficiency of heat dissipation is not high because the heat conductivity of silicon oxide (about 1.4 W/mK) is two orders smaller than that of silicon (about 150 W/mK). This results in a problem that a sufficient level of heat dissipation effect cannot be obtained.